Static semiconductor RAM devices include a multiplicity of memory cells, wherein each memory cell stores a single bit of data so long as the RAM device remains energized. Static memory differs from dynamic memory in that data stored in the static memory remains valid without the need for refreshing. A continuing need exists for memory cells that can be implemented in smaller semiconductor die area. Smaller memory cells lead to semiconductor memory circuits which are capable of storing more data and are often faster devices. However, shrinking a memory cell without impairing stability, speed, yield or power consumption parameters is a difficult task.
FIG. 1 shows a schematic diagram of conventional variations of a static RAM (SRAM) cell. A basic memory cell 10 includes cross-coupled drivers 12. Each driver 12 has an I/O port 14, and drivers 12 together form a bistable storage element that stores a single bit of data. Pass transistors 16 couple I/O ports 14 to bit (B) and bit-bar (B) lines 18 and word lines (W) 20. Drivers 12 couple to Vss, and loads 22 couple between Vcc and drivers 12. Conventional variations in memory cell 10 differ from one another in their configurations for loads 22.
One prior art memory cell 10 uses resistors 24 for loads 22. When resistors 24 are used for loads 22, memory cell 10 is referred to as a four-transistor memory cell. Lower valued resistors 24 are desirable in order to improve yield, reliability, and area requirements. In addition, lower valued resistors 24 promote stability and greater immunity to noise when the drive transistors 12 for which they are loads are in "off" states. Unfortunately, higher valued resistors are desirable to reduce standby power consumption and to improve the speed of operation. Moreover, higher valued resistors promote stability and greater noise immunity when the drive transistors 12 for a which they are loads are in "on" states.
No single resistor value of a four-transistor memory cell promotes stability and noise immunity for both states of drive transistors 12. Further, as cell size shrinks, reduced power consumption becomes more important for purposes of heat dissipation because a given amount of power is dissipated over the cell's die area. Accordingly, the use of resistive loads in memory cell 10 leads to undesirably high standby power consumption and to worsened stability, speed, yield and/or reliability characteristics as cell size shrinks.
Another prior art memory cell 10 uses P-channel transistors 26 for loads 22. When P-channel or other transistors are used for loads 22, memory cell 10 is referred to as a six-transistor memory cell. P-channel transistors 26 solve many of the problems associated with resistors 24. P-channel transistor 26 memory cell implementations consume a moderately low amount of power and can be manufactured reliably. However, P-channel transistors 26 require an undesirably large die area. A P-channel transistor typically requires the formation of an N-well diffusion into the substrate in which the P-type drain and source diffusions are formed, and this N-well diffusion occupies a large area. Moreover, the channel itself is typically larger than in a corresponding N-channel transistor due to lower hole mobility for the P-channel device.
In addition, P-channel loads 26 cause the memory cells to experience current spikes for brief instants when both drive and load transistors are at least partially in their "on" states. The current spikes contribute to an undesirable package resonance effect and slow memory cell access, particularly for write operations. Accordingly, while P-channel transistor loads 26 work well for many purposes, P-channel transistors 26 are too large for use in small memory cells and experience excessive current spikes which slow operation and increase power consumption above theoretical levels.
Another prior art memory cell 10 uses depletion mode, N-channel transistors 28 for loads 22. Depletion mode, N-channel transistors 28 are smaller than P-channel transistors 26, but experience problems similar to those experienced by resistors 24. In particular, depletion mode transistors 28 are characterized by high power in their "off" state. Processes which minimize this power consumption parameter cause yield problems. Moreover, a body effect causes a depletion mode transistor to continuously, rather than discretely or distinctly, transition between "on" and "off" states. This continuous transition feature leads to undesirable switching noise, current spikes, and slow access times.
Another prior art memory cell (not shown) uses a tunnel diode as a storage element. A tunnel diode has two distinct operating regions. A first operating region occurs at a low forward voltage, typically less than 0.1 volts. A second operating region occurs at a higher forward voltage, typically greater than 0.6 volts. The region between these two operating regions (i.e. typically around 0.1-0.6 volts) is an unstable region in which the device exhibits a negative resistance. A tunnel diode acts as a storage element by distinctly operating in either the first region or the second region. While a tunnel diode storage element exhibits desirable size and power characteristics, it is not a stable device. In other words, the tunnel diode storage element too easily switches to its other region of operation when a device incorporating such elements experiences a range of temperatures and read-write operations over time, as occurs in normal memory circuits. Because of stability problems, memory cells using tunnel diodes as storage elements have not proven themselves to be commercially viable.